Topological and Geometric Data Analysis (TGDA) for Materials and Interfaces
From predicting biodegradable polymers, to modelling defects and scaling the simulation of rough material interfaces, topological and geometrical methods have found their calling! At the same time, our EMOS framework is expanding, with modular graph structures offering unlimited possibilities to design custom material discovery pipelines.
During the summer I will be presenting my work on mapping the configuration space of colloidal nanoparticles at the AI4X conference in Singapore (15-18 June), and at the Foundations of Computational Mathematics (FoCM2026) conference in Vienna (8-11 July).
Dr. Alex Keros
Can Machine Learning Help Design Better Energy Harvesters?
Energy harvesters such as triboelectric nanogenerators (TENGs) are gaining increasing attention as sustainable power sources for wearable electronics, healthcare devices, and self-powered sensors. However, predicting the electrical output of TENGs remains a major challenge because their performance arises from complex, nonlinear interactions between material properties, device architecture, and operating conditions. In addition, the field still lacks reliable empirical or surrogate models that can capture these coupled effects in a generalisable way.
Over the past few months, I worked on addressing this challenge by developing a multiscale, machine-learning-based surrogate modelling framework for contact–separation TENGs. This effort led to the development of PhyTENG, a physics-informed ML framework that combines curated experimental data with materials descriptors obtained from open-source databases and auxiliary ML models. These descriptors provide scientifically meaningful information such as electronic, dielectric, and triboelectric properties that helps the model move beyond simple categorical representations of materials.
As part of this work, I also manually curated an experimental dataset of around 450 data points from around 28 published studies, covering a broad range of TENG materials, device configurations, and operating conditions. The resulting framework was found to outperform conventional ML approaches based on categorical features and also demonstrated stronger generalisability, including on previously unseen material systems.
This work has recently been accepted and published in Nano Energy, and can be accessed with this link: https://www.sciencedirect.com/science/article/pii/S2211285526003083
Dr. Shashank Mishra
agenticSizing: Role-Based LLM-Guided Analog Circuit Optimization
Over the past few months, I have been developing agenticSizing, an LLM-guided framework for analog IC sizing that combines structural circuit understanding, knowledge-based reasoning, and simulation-in-the-loop optimization. The aim of the project is to move beyond conventional “flat” parameter optimization approaches by incorporating circuit hierarchy and functional intent directly into the optimization process.
Recent work has focused on developing a more modular and interpretable optimization workflow that better aligns with practical analog design methodologies. Instead of relying solely on black-box search strategies, the framework uses circuit structure and prior knowledge to guide optimization decisions while continuously validating results through simulation feedback. This approach aims to improve transparency and efficiency in the optimization process and provide a more flexible foundation for handling different circuit topologies and design objectives.
Initial experiments have shown encouraging results in terms of interpretability and adaptability across different design scenarios. Ongoing work is focused on improving the robustness of the framework, particularly in relation to structural decomposition, optimization stability, and consistency across varying circuit configurations.
Dr. Yijia Hao
Spiking Neural Networks and Neuromorphic Hardware for Efficient On-Chip Learning
My recent work focuses on spiking neural network algorithmic exploration, on-chip learning hardware, and algorithm–architecture co-design for neuromorphic computing systems. The broader goal is to develop energy-efficient and flexible hardware platforms that can support brain-inspired learning algorithms while maintaining high-speed execution.
I have recently designed an SNN implementation on the ZCU104 platform that integrates both software and hardware cores. In this system, the software core is responsible for controlling the programmable logic core, allowing the overall architecture to remain highly flexible while still benefiting from hardware-level acceleration. This approach enables rapid experimentation with different SNN configurations and learning mechanisms, while ensuring efficient execution on FPGA-based hardware.
I am currently working on the design of neuromorphic hardware for an SNN that uses the Tempotron learning algorithm. Since Tempotron is generally used for binary classification, my work explores how this approach can be extended towards multiclass classification. This involves investigating suitable algorithmic modifications, hardware-aware design choices, and efficient implementation strategies for scalable on-chip learning.
Through this research, I aim to contribute to the development of intelligent neuromorphic systems that combine adaptability, efficiency, and hardware-level performance, supporting future edge-AI and brain-inspired computing applications.
Dr. Ali Siddique
From Natural Language to Hardware: The LaMDA Framework
Over the past several months, I have led the development of LaMDA, a language model–assisted electronic design automation framework that integrates with industrial design environments such as Cadence Virtuoso, Keysight ADS, and AMD Vivado. Unlike general-purpose AI systems, LaMDA is designed with built-in knowledge of engineering workflows, including design rules, file formats, and tool-specific behaviour. This allows it to generate valid design files and accurately interpret outputs from simulation, synthesis, and place-and-route processes.
My primary technical contribution has been LaMDA-FPGA, a subsystem that connects large language models directly with the AMD Vivado toolchain for FPGA design automation. LaMDA-FPGA enables engineers to describe hardware functionality in natural language and receive automated hardware description language generation, synthesis management, constraint handling, and iterative optimisation guided by power, performance, and area reports. By combining AI-driven generation with tool-aware validation and feedback, the framework reduces manual effort while maintaining compatibility with real-world engineering workflows.
The preprint is available at https://arxiv.org/abs/2601.14098, and the tool is available at https://github.com/aprilaihub/LaMDA.
Dr. Cristian Sestito
A block diagram of the LaMDA framework running the analogue design flow:
Can Large Language Models Design RF Circuits?
Over the past few months, a major focus of our research has been the application of large language models (LLMs) within Electronic Design Automation (EDA). This has led to the development of LaMDA, a flexible language model-assisted EDA framework designed to support digital, analogue, and Radio Frequency (RF) design workflows. By combining LLM capabilities with commercial EDA tools, the framework enables circuit generation. A pre-print of LaMDA is currently available here: https://arxiv.org/abs/2601.14098.
My contribution to the project has focused on the RF design. The proposed framework operates through an automated iterative workflow in which an initial circuit design is generated from natural language requirements by an LLM. This design is then refined through repeated optimisation cycles using automated feedback derived from tool-specific simulations. The workflow has been evaluated using representative case studies to assess its effectiveness and reliability. While expert oversight remains important for validation and final decision-making, the approach demonstrates how AI-assisted automation can significantly accelerate design iteration and testing processes.
Dr. Panagiota Kontou
LLM for Analogue Integrated Circuit Design
My recent research focuses on the application of large language models to analogue integrated circuit design. I have developed LaMDA-Analog, an AI-assisted design automation framework that integrates with Cadence Virtuoso and Cadence Spectre to support automated circuit generation, simulation, and optimisation.
In this framework, a designer specifies circuit requirements in natural language, such as gain, bandwidth, phase margin, noise, and power consumption. The system then generates transistor-level netlists, creates simulation testbenches, performs parameter sweeps, and analyses the simulation results to iteratively refine the design. The workflow incorporates engineering knowledge, including simulator syntax, device sizing conventions, and analogue performance metrics, enabling the generation of valid and executable design files.
This work demonstrates how large language models can significantly reduce manual effort and accelerate analogue circuit design and optimisation while remaining fully compatible with industrial EDA workflows.
Dr. Pratibha Verma
AI-Driven Optimisation of GaN Device Design and Reliability
Designing advanced semiconductor devices such as GaN transistors typically relies on detailed physics-based simulations. While these models are accurate, exploring different device designs and understanding performance trade-offs can be time-consuming, especially when multiple non-ideal effects are involved.
My research focuses on combining physics-based device modeling and simulation with machine learning to accelerate this process. Using simulated datasets from advanced GaN devices, I aim to develop data-driven models that can predict key performance metrics such as threshold voltage, on-resistance, and reliability behaviour under different design conditions.
A later stage of this work includes analysing how non-idealities—such as self-heating, traps, and access resistance-impact device performance. By learning patterns from simulation data, machine learning models can help identify critical design sensitivities and guide optimisation more efficiently than traditional trial-and-error approaches.
This approach does not replace modeling and simulation, but complements it. The goal is to reduce design iteration time and enable faster exploration of the device design space, ultimately supporting more efficient and reliable next-generation semiconductor technologies.
Dr. Zarak Bhat
Turning Device Literature into AI-Guided Design Insight
Scientific papers contain a rich history of electron device experiments, but much of this knowledge remains difficult to reuse because key results are often buried in figures, tables and scattered text. My recent work focuses on making this information more accessible for AI-assisted device design, with the aim of helping researchers move from manual interpretation towards structured, traceable data that can support optimisation.
A major part of this work has been the development of a literature data-extraction workflow for semiconductor devices. The goal is to recover useful information such as device geometry, processing conditions, electrical characteristics and performance metrics from selected papers, and convert them into benchmark data that can be checked, reused and extended. This creates a foundation for modelling relationships between fabrication choices and device behaviour.
Alongside this, I completed an initial optimisation study on IGZO thin-film transistor selectors for resistive memory systems. Using data extracted from the literature, machine-learning models and Bayesian optimisation were used to explore trade-offs between high drive current, low leakage and suitable threshold voltage.
A further direction is now emerging around flexible electronics and custom integrated-circuit design, where device-level optimisation connects to future mixed-signal, neuromorphic and hardware-accelerated systems. Together, these activities support a broader workflow linking literature knowledge, AI-guided optimisation and next-generation hardware design.
Dr. Chandrabhan Kushwah
PRAMANA: Towards an Autonomous Hardware Verification Assistant
Getting a hardware chip right before it is manufactured is one of the most demanding tasks in engineering. Even a small error in the logic, a single flipped condition in thousands of lines of code, can make a device fail in the field. The traditional answer is a long, manual verification effort that consumes more than half of a typical design project's time and cost.
PRAMANA — Proof-centric RTL Agentic Model for Assurance, Narrative, and Automation, taking its name from the Sanskrit word for proof and means of knowledge, is our framework for automating this process. Under a delivered project on accelerating digital verification with generative AI for defence applications, we have already implemented three co-operating AI agents: one that measures and improves the quality of a verification property-set by injecting realistic faults and scoring how many are caught; one that profiles a design's structural complexity and selects the best solver automatically; and one that reads a formal failure report and produces a concise, human-readable explanation of what went wrong and why. Tested across diverse hardware designs, the framework reliably catches the large majority of injected faults and explains failures accurately, results that previously required significant manual effort from a verification specialist.
The long-term goal is broader: PRAMANA aims to cover every activity in the digital verification loop; from test stimulus generation and environment modelling through simulation, emulation, and coverage closure, as a fully closed-loop agentic system. Formal verification is the first and deepest piece; each remaining activity in the loop is a planned next step.
Dr. Ramesh Krishnamurthy
Generative AI-assisted methodologies for FPGA–GPP heterogeneous systems, intelligent hardware design automation, and AI-driven verification frameworks
My recent research has focused on the development of generative AI-assisted methodologies for FPGA–GPP heterogeneous systems, intelligent hardware design automation, and AI-driven verification frameworks. The work explores how Large Language Models (LLMs), retrieval-augmented generation (RAG), and automated design flows can be integrated into Electronic Design Automation (EDA) workflows to improve system performance, resource utilisation, and design productivity.
As part of a cross-pillar research effort, I am investigating AI-assisted task allocation for FPGA–GPP heterogeneous systems, where generative AI produces explainable hardware–software partitioning strategies from user requirements and HLS/Verilog designs to improve latency and FPGA resource utilisation. In parallel, I am developing generative AI-driven design and verification frameworks that automatically generate hardware designs, verification environments, and software reference models from high-level specifications. The workflows integrate synthesis, simulation, and validation feedback into closed-loop RAG systems, enabling continuous improvement in design quality, correctness, and synthesizability.
Overall, the research aims to develop intelligent and self-improving EDA toolchains that combine AI-assisted design generation, heterogeneous system optimisation, and automated verification for next-generation ASIC and FPGA design workflows.
Dr. Rain Zhao
