Seed Funding Seminar - AI-Enhanced Reliability Optimization in SRAM Cells under Process-Induced Variability

Abstract:

As technology scales down, fabrication inconsistencies create process variability, affecting SRAM stability and increasing error rates. However, there is no known method to address this challenge. The targeted problem can be formulated into a computationally expensive design optimization problem. To invent a solver, machine learning methods will be compared and selected to map physical parameters with SRAM performance metrics. AI-based heuristics optimization techniques will be employed to search for optimal physics parameters. Model management methods will be investigated to make the machine learning and heuristics optimization methods work harmoniously. This AI-based solution will influence memory cell design for advanced processes by significantly improving yield and reducing costs.

Prof. Bo Liu:

Bo Liu received the B.Eng. degree from Tsinghua University, China, in 2008 and the Ph.D. degree from University of Leuven (KU Leuven), Belgium, in 2012. Currently, he is a Professor of Electronic Design Automation at University of Glasgow. He is a Fellow of IET and a Senior Member of IEEE. His research focuses on novel data-driven optimization and machine learning algorithms for electronic design and their real-world applications, including antennas, analog/RF ICs, and filters.

He published the first industrial practical machine learning-assisted global optimization algorithm for antenna design in 2014. He is the inventor of the SADEA series for AI-driven antenna design, the ESSAB series for AI-driven analog IC design, and the GASAPD series for AI-driven RFIC design, which are well recognized in the field. More information can be found at https://www.gla.ac.uk/schools/engineering/staff/boliu/

Dr. Ankit Dixit:

Ankit is working as a Research Associate with the DeepNano group at the University of Glasgow, United Kingdom. He completed his Master’s and PhD in Electronics and Communication Engineering at the Indian Institute of Information Technology, Design and Manufacturing (IIITDM), Jabalpur, India.

His research focuses on semiconducting nanoelectronic device simulation and modelling, particularly advanced transistor architectures such as Gate-All-Around (GAA) FETs and FinFETs. He is also actively involved in the optimization of device performance using machine learning techniques, integrating computational intelligence with nanoscale device engineering. He is a member of several professional societies, including IEEE, ISTE, and IETE and published numerous research articles in reputable national and international journals and conferences.