Seed Funding Webinar - SECDA-DSE: Automated Design Space Exploration of FPGA-based Accelerators using LLMs

Abstract:

Large Language Models (LLMs) are becoming an essential component of modern Artificial Intelligence (AI) systems across many application domains. However, designing FPGA-based accelerators for AI workloads remains a complex and iterative process that requires expert knowledge and extensive manual fine-tuning. This results in long design cycles and limits accessibility for non-specialists. To address these challenges, we propose SECDA-DSE, an automated design space exploration framework that leverages LLMs to efficiently navigate hardware design spaces and generate optimised accelerator architectures. SECDA-DSE extends our existing SECDA hardware-software co-design methodology by integrating LLM-driven automation, significantly streamlining the development of new hardware accelerators. Our approach employs open-source LLMs that can be iteratively fine-tuned using accelerator design datasets, enabling continuous improvement of the exploration process. By combining automated reasoning with domain-specific knowledge, SECDA-DSE reduces design effort, accelerates development time, and improves the performance and scalability of FPGA-based AI accelerator designs.

Dr. José Cano:

José Cano is a Reader (Associate Professor) in the School of Computing Science at the University of Glasgow where leads the Glasgow Intelligent Computing Laboratory (gicLAB). His work sits at the intersection of computer architecture, computer systems, compilers, machine learning, and security, with a strong focus on hardware-software co-design for efficient AI/ML on mobile and embedded edge devices. He is PI at the University of Glasgow on the Horizon Europe project dAIEDGE and the UKRI APRIL AI Hub project SECDA-DSE, and Co-I on the UKRI project IDEAL; he was PI on the EPSRC PETRAS project MAISE, and Co-I on the UKRI "Digital Security by Design" projects AppControl and Morello-HAT. José has published over 60 peer-reviewed papers and secured more than £1.9M research funding as both PI and Co-I. He received his PhD from the Universitat Politècnica de València in 2012; and is a Senior Member of IEEE and ACM, and a member of HiPEAC.

Dr. Jude Haris:

Jude Haris is a post-doctoral researcher at the School of Computing Science at the University of Glasgow, where he completed his PhD on “Hardware-Software Co-Design of FPGA-based Neural Network Accelerators for Edge Inference”. His research interests lie in Computer Architecture with a special focus on hardware software co-design of FPGA-based AI Accelerators. His current work has been focused on developing FPGA-based hardware accelerators for DNN inference on edge computing devices. During his PhD, he proposed and developed the SECDA methodology and the SECDA-TFLite platform, which is currently used by the community to develop and test new accelerator designs for edge computing devices.