APRIL: Research

Main Pillars

To ensure we maintain, and exceed, our position in this market, we need to bring the power of AI to the 5 main pillars of the electronics supply chain:

P : 1

PILLAR ONE

Materials Discovery

Pillar 1 Lead

Prof. Jacqueline Cole

Pillar 1 Lead

Prof. Subramanian Ramamoorthy

Develop AI tools that can optimise material compositions for engineering electron devices with desirable behaviours, accelerating materials discovery and their use in sustainable manners. This spans from "AlphaFold-style" property prediction to automated post-production assessment of e.g., defect detection or physical properties.

Materials discovery is key for the development of next-generation electron devices. We pioneer tools to advance material science for electronics engineering. From Electronic Materials Operating System (EMOS), the one-stop-platform that curates material databases, generators, and predictors for crafting custom material discovery pipelines, to topological methods for characterizing atomic structure and material behaviour, we develop novel data-driven methods to investigate material properties and structures. Our cutting-edge AI models, from the gradient-boosted electronic property predictors to the property conditioned synthesis-aware generative solutions, provide efficient ways to predict future-defining materials.

P : 2

PILLAR TWO

Device Design

Pillar 2 Lead

Prof. Bipin Rajendran

Pillar 2 Lead

Prof. Merlyne De Souza

Establish AI-based systems that can design and execute experiments in search of the best manufacturing parameter settings to create electron devices with optimum performance and yield. This would immensely speed up the "process development" procedure that takes a new device to the market, delivering more efficient, reliable and sustainable products quicker. This spans from optimal "device recipe" prediction to automated testing and yield assessment.

Device Design aims to build AI‑driven systems that design and execute experiments to discover optimal device recipes and manufacturing parameters for high‑yield, high‑performance electron devices. We have been developing a modular, cloud‑ready pipeline that automatically curates experimental FinFET data from the literature—combining open‑source tools, OCR, rule‑based and LLM‑assisted parsing, unit normalization, semantic filtering, and a custom scholarly search engine—to scale trustworthy datasets for benchmarking and design. In parallel, we are building an ML framework that learns latent features from literature‑extracted simulation and experimental data to predict key metrics and enable inverse design, reducing trial‑and‑error. Ongoing efforts span TCAD calibration, physics‑informed optimal control, and LLM‑based verification. Together, these developments advance data‑driven decision‑making, improve reproducibility, and accelerate automated testing and yield assessment—bringing more efficient, reliable, and sustainable devices to the market.

P : 3

PILLAR THREE

Circuit & System Design

Pillar 3 Lead

Prof. Christos Bouganis

Pillar 3 Lead

Prof. Michael O'Boyle

Introduce AI into commercially available circuit design tools to autonomously synthesise new circuit topologies and system architectures to drastically cut the design time, and optimise the cumbersome transfer of known topologies into new complementary metal-oxide semiconductor (CMOS) technologies. It spans human-AI digital circuit co-design (using natural language specs) to automated circuit topology discovery and place & route optimisation for building efficient chips.

The AI for Circuits and System Design Automation Pillar advances intelligent methods to streamline the design of complex electronic circuits and systems. A major ongoing project is the development of a toolchain powered by large language models (LLMs) to support analogue, digital, and radio frequency (RF) circuit design. This toolchain integrates with commercial electronic design automation (EDA) platforms, facilitating design from natural language specifications so users can express their intent conversationally. By incorporating feedback from power, performance, and area (PPA) analysis throughout the workflow, the approach helps designers make informed decisions, optimise their work efficiently, and meet target specifications. Leveraging state-of-the-art AI, the project aims to accelerate the design process, reduce errors, and expand the capabilities of automated circuit design and optimisation.

P : 4

PILLAR FOUR

Testing & Verification

Pillar 4 Lead

Prof. Máire O'Neill

Pillar 4 Lead

Prof. Kerstin Eder

Embed AI principles in testing to reduce the required time and to predict what to test/when. Spans from improving scenario coverage in certification tests across devices/systems to automatically deciphering underlying physical mechanisms in emerging beyond-CMOS devices.

Pillar 4 focuses on Electronics Testing and Verification Automation by embedding AI principles to streamline testing processes and improve prediction accuracy. The goal is to reduce verification time and increase efficiency by enhancing scenario coverage in certification tests across diverse devices and systems, extending even to automatically deciphering physical mechanisms in emerging beyond-CMOS devices.

One ongoing project is a workflow that automates circuit design and testing using commercial EDA tools, enabling faster Radio Frequency (RF) design. By leveraging a Large Language Model (LLM), users can describe the circuit they want, which is then automatically implemented and tested in commercial EDA tools, thus making the process both faster and accessible, even for those unfamiliar with the tool. Building on this, we are also developing AI-driven verification methodologies for digital designs (SoCs/ASICs). This includes using machine learning to guide test generation, accelerate coverage closure, and reduce redundant simulation cycles within traditional-based testbenches. Our approach treats verification not only as a pass/fail process but as a dynamic loop where AI learns from coverage gaps and failure patterns to suggest the next best tests.

By combining these strands, RF design automation, functional verification acceleration, and beyond-CMOS testing, Pillar 4 aims to create a holistic AI-powered verification ecosystem that can adapt across technologies, reduce engineering effort, and shorten time-to-market for next-generation systems.

P : 5

PILLAR FIVE

Modelling

Pillar 5 Lead

Prof. Vihar Georgiev

Pillar 5 Lead

Prof. Rishad Shafik

Build "digital twins" for modelling device/systems performance, with input from automated testing routines. This would significantly boost the rate at which new semiconductor technologies mature to a level usable by circuit designers. This pillar spans from automated process development for new and emerging semiconductor devices to efficient modelling of complex systems.

Artificial Intelligence (AI) is revolutionizing industries worldwide, delivering unprecedented productivity gains across diverse sectors, from healthcare to manufacturing. Indeed, several machine learning (ML) methods have significantly advanced semiconductor industry as well, particularly in last few years, by providing sophisticated methods for analysing the performances of the emerging devices. In these emerging devices, CMOS is the current dominant technology for microprocessors, and beyond CMOS refers to future technologies that aim to overcome CMOS's limitations in scaling, power, and speed. Generally, the tremendous increase of computational power of integrated circuits is supported by the continuing miniaturization of semiconductor devices’ feature size. In this direction, our investigation is going on with the ML-guided design and optimization of ultra-scaled transistors. In parallel, we also scrutinize how AI can enhance the understanding and optimization of skyrmion-based systems. This Skyrmions are topologically protected spin configurations typically observed at the nanoscale in magnetic material.

Core Capabilities

The vertical pillars' structure of APRIL is complemented by a horizontal structure of fundamental, cross-cutting capabilities that shall underpin our ability to deliver each pillar. Most hub tasks will draw upon these, hence having highly professional/specialized capability in all (and flexibly allocable) is a key productivity-enhancing ingredient of the APRIL AI Hub.

C : 1

CAPABILITY ONE

Data collection

Running a successful AI model requires the ability to collect data that is designed appropriately for AI to digest. This is applicable to all pillars and having specialised knowledge on doing precisely that is of paramount importance.

C : 2

CAPABILITY TWO

AI model selection

The vast array of AI models is expanding at an incredibly fast rate and knowing which model to choose for different tasks is critically important. This enables APRIL to keep abreast with and push the boundaries of state-of-the-art AI models. It is especially relevant when considering generative models and techniques (from task-specific output generation to general text, like GPT).

C : 3

CAPABILITY THREE

AI model training

Training can be extremely computationally intensive, as well as requiring specialised techniques in cases where the amount of training data is minimal. It is essential to be able to advise on the best AI, machine learning (ML), statistical, and high performance computing techniques to optimise training.

C : 4

CAPABILITY FOUR

System integration

Transforming research into useable technology requires significant attention to "containers and interfaces", i.e., software packages that can choreograph multiple modules, extract meaningful insights, and present friendly interfaces to users inputting complex or big data. This is key to translating technology and is a fundamental axis of our impact strategy.

C : 5

CAPABILITY FIVE

Data security

There is a significant need to evaluate the suitability of system architectures, specifications, and implementation methodologies for trusted, responsible, explainable and secure AI solutions. Focusing on cybersecurity and trustworthy systems in safety-critical industries is important for our impact strategy to protect against attacks, interpret predictions, and better understand AI systems.

Projects

APRIL will deliver I0 interconnected research projects (2 per pillar) using the PDRA/F time available to the hub. These have been chosen to build core, general-purpose capability within the hub, shall span the duration of the proposed project (Y1-5) and will be led by UoE collaboratively with all academic leads from across the UK.

Research

Main Pillars

Core Capabilities

Projects

Delivering World-leading AI research in electronics & semiconductors